Project Management with Make

Steven J Zeil

Old Dominion University Dept. of Computer Science

Jul. 16, 2005

Contents:

1 Symbols

2 Default Rules

3 Common Conventions

4 Creating a Makefile

5 Is It Worth It?

(A printable version of this document is available here.)

When you begin to develop projects that involve multiple files that need to be compiled or otherwise processed, keeping them all up-to-date can be a problem. Even more of a problem is passing them on to someone else (e.g., your instructor) and expecting them to know what to do to build your project from the source code.

The Unix program make is designed to simplify such project management. In a makefile, you record the steps necessary to build both the final file (e.g., your executable program) and each intermediate file (e.g., the .o files produced by compiling a single source code file).

We say that a file file1 depends upon a second file file2 if the file2 is used as input to some command used to produce file1.

When the make program is run, it then checks to be sure that all of the needed files exist, and that each needed file has been updated more recently than all of the files it depends upon. The key bits of information in a makefile, therefore are

For each file, a list of other files it depends upon, and
The command used to produce the dependent file from the files it depends upon.

A makefile may also include various macros/abbreviations designed to simplify the task of dealing with many instances of the same commands or files.

Suppose that we are engaged in a project to produce 2 programs, progA and progB. progA is produced by compiling files utilities.c, progA1.cpp, and progA2.cpp and linking together the resulting .o files. Program progB is produced by compiling file utilities.c and progB1.cpp and linking together the resulting .o files. All of the .c and .cpp files have #include statements for a file utilities.h. Also, both of the .cpp files have an #include statement for a file progA1.h.

Here is a makefile for this project. This file should reside in the project directory, and should be called “Makefile” or “makefile” .

progA: utilities.o progA1.o progA2.o g++ -g -DDEBUG utilities.o progA1.o progA2.o mv a.out progA progB: utilities.o progB1.o g++ -g -DDEBUG utilities.o progB1.o mv a.out progB utilities.o: utilities.c utilities.h g++ -g -DDEBUG -c utilities.c progA1.o: progA1.cpp utilities.h progA1.h g++ -g -DDEBUG -c progA1.cpp progA2.o: progA2.cpp utilities.h progA1.h g++ -g -DDEBUG -c progA2.cpp progB1.o: progB1.cpp g++ -g -DDEBUG -c progB1.cpp

The key information in a makefile consists of a variety of rules for producing “target” files. Each target rule begins with a single line containing the name of the file to produce, a colon, and then a list of all files that serve as inputs to the commands that produce the file. Following that are any number of command lines that give the Unix commands to actually produce the file. Each command line starts with a “Tab” character (invisible in this listing).1

A common mistake in preparing makefiles is to use ordinary spaces instead of a tab character in front of these command lines. The usual result of this mistake is the error message

Makefile:N *** missing separator

where N is the approximate line number where the error occurs. The "separator" here refers to the fact tha make expects each rule to be separated from the others by one or more empty lines. A line that starts with a space (instead of a tab) is assumed to be a new rule. Since command lines are not separated from the rest of the rule, a command line starting with a blank instead of a tab appears to make as a new rule starting up without an empty line separating it from the previous rule.

Suppose that, with just this Makefile and the various source code files in your directory, you issued the command

make progB

make reads the Makefile and notes that progB depends upon utilities.o and progB1.o. Since neither of these files exists, make sets out to create them. utilities.o depends upon utilities.c and utilities.h. Since these files exist and do not themselves depend upon anything else, make will issue the command to create utilities.o from them. This command is the “standard” command for making a .o file from a .c file:

gcc -g -DDEBUG -c utilities.c

Next make looks at progB1.o. It depends upon progB1.cpp which exists and does not depend upon anything else. So make uses the standard command for C++ files:

g++ -g -DDEBUG -c progB1.cpp

Now that both .o files have been created, make proceeds to build its main target, progB, using the command lines provided for that purpose:

g++ -g -DDEBUG utilities.o progB1.o

and the progB program has been created.

Now suppose that we immediately give the command

make progA

(or just “make” , since by default make builds the first target when none is explicitly given). Then the following commands would be performed:

g++ -g -DDEBUG -c progA1.cpp g++ -g -DDEBUG -c progA2.cpp g++ -g -DDEBUG utilities.o progA1.o progA2.o mv a.out progA

Note that utilities.c is not recompiled, because make would notice that utilities.o already exists and was created more recently than the last time when either utilities.c or utilities.h was changed.

If you want to test your makefile without actually performing the commands, add a -n option to your command (e.g., make -n progB) and make will simply list the commands it would issue without actually doing any of them.